[SGVLUG] Linux Sonoma (Centrino) Support

[Dustin]

On Tue, 20 Sep 2005, Chris Smith wrote:

> On 9/20/05, Dustin <laurence at alice.caltech.edu> wrote:
> > On Tue, 20 Sep 2005, Chris Smith wrote:
> > Hmm, I thought Sony Vaios were fairly well liked among Linux folk?
> 
> We're masochists. ;-)

Oh, right, I did say Linux types.  What was I thinking? =8-O

> ...I think the poser value of having a flashy
> looking laptop won out over the "how much can I do with Linux?"
> factor.

	me->CrossOffList("Sony Vaio");

I'm not that into form over function. :-)

> > Whether true or not, and putting on my most prejudiced hat, I always like
> > to imagine that the big mistake was in thinking that the purchasers of
> > high-end servers somehow care about that amusing company that makes those
> > little chips for home computer toys. :-)
> 
> Yeah, I don't think that was really that much of a mistake.

Sssh.  I'm enjoying the thought too much. :-)

> about such things are very much aware of it. We just aren't that
> excited because when it comes to integer performance, the x86 chips
> still beat it.

Recall in another life I was a physicist.  Floating point speed gives me a 
warm feeling all over. :-)

> the number of transistors needed for doing translation has remained
> essentially fixed, while transistor budgets have followed Moore's Law.

That's the essential point, thanks.  I like scaling law arguments. :-)

> Yeah, and when you look at the PPC ISA, it's only slightly less ugly than x86.

I haven't really.  I don't have a PPC chip to my name, for one thing.  I 
recall MIPS was quite clean, and I kind of think Alpha was reasonable 
though now that I think of it I don't know why I think that.

> > I seem to recall something like that.  If all that cache wasn't so
> > expensive...all that L2 cache seems to be a strength of the P-M, too, so
> > there's more continuity for ya.
> 
> >From what I understand, cache is actually fairly cheap compared to
> just about anything else you can do with your transistor budget. They
> tend to be far more compact and fault-free than other parts of a chip.

My understanding was that the cache was what killed the PPro in terms of
price, but it had some funky system where the cache was bonded onto the
CPU or some such wierdness that drove the cost up.  It might not have any
relevance to current chips, but given that the HPC guys tell me that
nothing really matters any more besides avoiding cache misses, I assume 
cache sizes will only go up, maybe faster than main memory.

> Having a shorter pipeline really, really helps. The P4's deep pipeline
> requires almost the same kind of challenging thinking needed for EPIC.

That was my understanding, but then I never got over losing the simplicity
of 6502 assembly.  Why would *anyone* need more than one 16-bit and two
6-bit registers anyway?

Epic?  I assume you don't mean the IRC client. :-)

Dustin